The present invention relates generally to a method for manufacturing a stack package, and more particularly, to a method for manufacturing a stack package capable of preventing a decrease in manufacturing yield and degradation in a semiconductor chip caused by thermal fatigue.
In the semiconductor industry, packaging technology is being continuously developed in order to satisfy the ongoing demand for miniaturization and mounting reliability. For example, the demand for miniaturization has accelerated the development of a package to the extent that the size of a package is very nearly that of the chip itself. The demand for mounting reliability has accelerated the development of techniques for improving the efficiency of a mounting task and the mechanical and electrical reliability of the device after mounting.
Development trends of electric and electronic appliances are clearly moving towards miniaturization and high functionality. In order to move towards smaller and multi-functioning devises various techniques are being researched and developed to provide semiconductor modules having high capacity. One technique used to provide a semiconductor module with high capacity is to supply a highly integrated semiconductor chip. Because of the desire for miniaturization, there is a limited area in a semiconductor chip in which cells can be formed. Thus, high integration of a semiconductor chip is realized by integrating an increased number of cells within the limited area of the semiconductor chip.
However, the high integration of a memory chip requires high precision techniques (such as a fine line width) and a lengthy development period. Because of these constraints, various stacking techniques have been proposed as another method for providing a semiconductor module having high capacity.
Currently, among the various stacking techniques, the most widely used stacking technique is a stack package that employs through-electrodes. In a stack package employing through-electrodes, stacked semiconductor chips are electrically connected to one another by the through-electrodes. The use of through-electrodes leads to a decrease in the size of the stack package and a shortening of signal transmission paths. Accordingly, stacked packages make it possible to accommodate the trend toward miniaturization and multi-functionality.
Stack packages employing through-electrodes can generally be divided into two types: A first type in which through-electrodes are formed in the chips of a wafer and all processes conducted prior to stacking are completed, and thereafter the chips are sawed and then stacked at a chip level; and a second type in which wafers, which are formed with through-electrodes and have undergone all processes conducted prior to stacking, are stacked at a wafer level, and thereafter sawing is conducted.
While not shown and described in detail, in the first type of forming a stack package, the manufacturing yield can be increased since semiconductor chips having already undergone a testing process can be stacked. However, in the first type, the number of processes needed for manufacturing the stack package increases. Further, when soldering is adopted for stacking semiconductor chips, problems are caused in that the arrangement of solder balls and a soldering temperature causes degradation in the semiconductor chips. In the second type of stack package, it is possible to decrease the processing cost and the processing itself can be simplified. However, all processes are conducted at a wafer level in the second type, and thus problems are caused in that the manufacturing yield of stack packages at the final stages of manufacturing is likely to abruptly decrease due if the manufacturing yield of the plurality of semiconductor chips of the wafers is poor during the initial stages of manufacturing.
Accordingly, when manufacturing stack packages having through-electrodes, a new technique for preventing the manufacturing yield from decreasing and semiconductor chips from degrading due to thermal fatigue is under high demand.